OH, NO! ATI R300 is coming...

[EvilDonnyboy]

Originally posted by [GDI]Raptor
I have heard that the R300 is on a 0.15micron process, that wil reduce the clock speed on a chip with over 100mil transistors,

It will be on a crazy 10-layer PCB to make up for it's relatively large gates. 10 layer PCB is very very expensive and hard to produce but it's likely R300 launch at a similar or cheaper price than what Parhelia laucned at ($399USD MRSP, street will be lower of course).

Not confirmed, but it's likely ATi will bring out a .13 "refresh" of R300 later, probably to compete with NV30 which will be on .13.

[Wombat]

It will be on a crazy 10-layer PCB to make up for it's relatively large gates. 10 layer PCB is very very expensive and hard to produce but it's likely R300 launch at a similar or cheaper price than what Parhelia laucned at ($399USD MRSP, street will be lower of course).

What? What the hell are you talking about? Raptor speaks of rumors of transistor count and processor size, and you say they'll use a high-layer PCB to compensate? Do you have <I>any</I> idea what you're talking about?

[Indiana]

Who says it's the R300.
It could also just be the RV250....

(the RV250 would be no reason for such a trailer, of course. But then those markting people sometimes do have crazy ideas)

[EvilDonnyboy]

Quality of PCB does contribute to how well a gpu can scale. It's the backbone to everything and can be a bottleneck if engineer's can't produce a noiseless enough path for all their traces.

[Wombat]

Which has <I>what</I> exactly to do with fabbing process? You still haven't answered that.

[Jon P. Inghram]

A 0.13 micron chip packs all it's connections into a tighter space, so you've gotta use more layers on the board to get all the traces out from the chip.

[Wombat]

Sorry, but no. First the connections go to the packaging, which then spaces everything out. Nothing to do with the PCB.

Next you'll be telling me the T-bred processors need more layers on the motherboard than the Palomino cores.

[Jon P. Inghram]

It sounded good at the time...

[EvilDonnyboy]

Layers of a motherboard are important as well. Engineer's must work hard to produce a noiseless path between every compenent. Dual-chaneel DDR systems are difficult in part becausej of the sheer number of traces needed to be drawn from each ddr slot to the northbridge to the cpu.

If there is not a noiseless enough patch between the gpu and other components of a video card, engineers may have to scale back clock-speeds to compensate. There are many many factors that can hinder and help gpu clock speeds. Die shrinks and ingenuitive layout and tracing are just a few. With more layers engineer's have more room to effectively layout all the traces, but at the cost of more difficult and expensive manufacturing.

[az]

EvilDonnyboy... take this advice from me: Don't argue with someone who knows way more about a subject than you do. You'll lose.

AZ

[Wombat]

EDB, it would really do you best to just be quiet. Stop trying to be an authority on subjects that you know nothing about.

[seether]

Just a question, not a statement...

In regards to noise - isn't that what wire width vs length for traces is all about? Regarding calculated optimum trace lengths and trace routes, isn't that what VIAs are for - to add the option of basically overlaping traces which are seperatd by VIAs to different components to save space, hence the option to add layers to a pcb depending on the complexity of the chips in order to map all connections (in other words... the purpose of adding layers is to allow more pseudo-direct bus routes laid over each other and seperated by VIAs instead of running an inefficient extra 30ft of wire zigzagging all over the place in order to keep far enough apart to prevent cross-talk all on the same layer)?

In regards to reasons for more layers on boards for smaller dies - since aside from the ability to fit more components in the same space, switching from .15 to .13 also allows for higher oscillating and/or lower voltage, wouldn't proportionally shorter buses be required for efficient communication? I don't see why the number of board layers would have to equate linearly to the complexity and die size of the chip, but instead more dependant on a combination of chip size and complexity, targetted speed, and the desired placement layout of other components on the same bus.

Not being a smartass, just sincerely curious.