Granite Bay MoBo

[Hati]

Xbitlabs posted infos on a Gigabyte mainboard based on Intels E7205 chipset.

http://www.xbitlabs.com/news/story.html?id=1037156407

I wonder how these board will be priced. Heard rumors that the boards will be very expensive (300 - 400€ in Germany)
With the P4 3.06GHz priced at about 800€ this hardware will remain a dream for me
Hati

[BuddMan]

Nice....damn, I hope that comes out before Christmas. If not I wonder if I should just wait....

[WyWyWyWy]

I wonder... will dual channel ddr333 be available shortly?

[Slougi]

Originally posted by WyWyWyWy
I wonder... will dual channel ddr333 be available shortly?

I doubt that is needed, as dual channel ddr 266 already saturates the p4 fsb afaik, even at 533 Mhz.

[Hati]

But isn't Intel supposed to crank up the FSB to 667 (?) MHz after the transition to Prescott and 90 nm process.
Heard there is a new chipset in the making (Springdale) for those CPUs that will come out next year.
Good old Intel 'change chipsets as often as you can' game again.
Hati

[WyWyWyWy]

Originally posted by Slougi

I doubt that is needed, as dual channel ddr 266 already saturates the p4 fsb afaik, even at 533 Mhz.

But hey! Some said ddr333 saturates 133fsb athlon too, then why is there ddr400? I think dual channel ddr333 is still needed for 533 fsb. Dual channel ddr400 is going a bit too far though...

[Hati]

Iwill boards are announced for 11/18
See:

http://www.ocworkbench.com/ocwbcgi/newspro/viewnews.cgi?newsid1037114882,99236,

Hati

[borat]

ddr333 does saturate the athlon because the athlon runs at 133 while the memory runs at 166 so the processor cannot take advantage of the extra memory bandwidth due to its fsb speed, unlock your xp however and you can crank the fsb up and up i rin mine at 192 mhz which gives a pretty significant boost in 3d.

[K6-III]

Originally posted by WyWyWyWy
I wonder... will dual channel ddr333 be available shortly?

Yeah...SIS655 chipset...

[PeTe]

SIS655 is the one Im waiting for. Released in next month.

Pe-Te

[DGhost]

Originally posted by WyWyWyWy


But hey! Some said ddr333 saturates 133fsb athlon too, then why is there ddr400? I think dual channel ddr333 is still needed for 533 fsb. Dual channel ddr400 is going a bit too far though...

1) because most of the computer enthusiast market is gullible enough to believe that the bigger number is better.

2) most of the computer enthusiast market would use the larger number to convince their friends that theirs is better (and the jealous people buy more shiz)

3) overclockers. DDR400 memory can be used in even a DDR333 board when doing heavy overclocks.

DDR400 acctually performs slower on the nForce2 than DDR333. the added latency of running the memory asychronously is more than enough to negate any benefit having the extra memory bandwidth might provide.

[Slougi]

Originally posted by DGhost
1) because most of the computer enthusiast market is gullible enough to believe that the bigger number is better.

2) most of the computer enthusiast market would use the larger number to convince their friends that theirs is better (and the jealous people buy more shiz)

3) overclockers. DDR400 memory can be used in even a DDR333 board when doing heavy overclocks.

DDR400 acctually performs slower on the nForce2 than DDR333. the added latency of running the memory asychronously is more than enough to negate any benefit having the extra memory bandwidth might provide.

I couldn't have put it better myself. Of course, since northwoods overclock so damn well, not overclocking them does not make much sense. So in a way it is needed, but what you must also think off is that info to and from ram is not the only thing that moves through the FSB.

[WyWyWyWy]

Hi,

I agree with you. But...

DDR400 acctually performs slower on the nForce2 than DDR333. the added latency of running the memory asychronously is more than enough to negate any benefit having the extra memory bandwidth might provide.

Why more mhz means less latency? I always wanted to know why... you know, most SDRAM can do CAS-2, but now most DDR can only do CAS-3, some better ones can do CAS-2.5...

Thanks.

[Marshmallowman]

most ddr 400 is cas 2.5 or higher with their other timing set conservatively by SPD.

good 333 is cas2 with some tight timings.

but if you get very good ddr 400, manually adjust timings and then use it synchronously you get very low latencies...but athlon boards that do 200 fsb(400ddr) are hard to find

[DGhost]

Originally posted by WyWyWyWy
Hi,

I agree with you. But...



Why more mhz means less latency? I always wanted to know why... you know, most SDRAM can do CAS-2, but now most DDR can only do CAS-3, some better ones can do CAS-2.5...

Thanks.

the higher the latency the more cycles are wasted waiting for the memory. because a memory chip can only do so much work because of its grade of manufacturing, many companies often release current generation memory modules running at higher speeds but also with higher latencies so there is very little increase in the amount of work it does. to make up numbers, if it was accessing the memory at 100 times a second but it was only on average taking 2 cycles to retrieve the memory, it would certainly do better that can access the memory 133 times per second but has to wait on average 3 cycles to get any data.

as far as running the memory asynchronously from the processor bus, take my lovely ascii art depicting the processor bus and memory bus:

Example #1 - Syncronous operation

-----_____-----_____-----_____-----_____ (processor)
-----_____-----_____-----_____-----_____ (memory)

Example #2 - Asyncronous operation
-----_____-----_____-----_____-----_____ (processor)
----____----____----____----____----____ (memory)

every time that the signal both rises (---) and falls (___) that is considered one cycle.

the first example shows busses running at 4hz (it could also be a very small amount of time on a 133mhz bus) ... if you were to request data from the memory, it would require 1 cycle to put the request, another cycle for the memory to get it (unlikely), and then the third cycle for it to retreive it. there is no waiting because the signals are all lined up and no problems ensue. it would take pretty much 3/4ths of a second to retreive the data.


Now consider the second example the the top bus is the processor bus running at 4hz) and the bottom bus is the memory bus running at 5hz, (which could also work as 166mhz if you added a ton and a half more cycles onto the end). when the processor requests a piece of data from memory, it takes one cycle. however, the memory is currently in the middle of its second cycle so it has to wait until its 3rd cycle to acctually retreive the data. however, when its done the processor has already spent its second cycle waiting on the memory and is half way through the third cycle waiting for the data. by the time the processor can get the data the bus on its 4th cycle, and a whole second has been wasted by the time the processor sees the data.

now, i'm not an EE and my understanding of this stuff is pretty basic, so i'm probably wrong on details and terms. this is just my understanding of it. someone who has more of a clue on the topic feel free to correct me.

I'm also sure there are ways around this by using memory caching, different memory timings (i was assuming only a 1 cycle latency on the memory access, on most memory types it is higher on certain types of reads), etc...