Oh no.....Geforce FX is coming!

[[GDI]Raptor]

hehe.....

Perhaps nVidia want's to start usinr RSN technology in ther NV30 chip.....

[thop]

ah the fairy demo, those were the glorious times

[Indiana]

Originally posted by Ali


Almost right, pity it only has 1 TMU per pipe though. I thought that was a given (the 2 TMUs I mean).

Ali

There were several threads on Beyond3D with very founded posts on why the 1TMU decision by ATI was a wise one. The arguments brought up there were so convincing that I would in fact have been really surprised if NVidia hadn't chosen the 8x1 design as well.

Expecially since even the 8x1 will likely be bandwidth limited with the 128Bit wide RAM in most of the game titles that we will se during the cards shelf live....

[DGhost]

Originally posted by Indiana


Expecially since even the 8x1 will likely be bandwidth limited with the 128Bit wide RAM in most of the game titles that we will se during the cards shelf live....

Hmm... do you have any proof or any sort of realistic reasoning to back it up? seriously?

a memory controller can be made to either underperform badly (like the Parhelias, and other G series card's), or it can be made to perform very well. NVidia has already proven in other ways that they know how to make very high performing memory controllers - look at the GeForce 4 MX cards. the major difference between the GF2MX and the 4MX came from the reengineering of the memory controller to incorporate better bandwidth saving techniques, a more efficent memory controller design, etc. Now with a memory controller that has half the bandwidth available to it, a GF4MX 440 can beat a GF3 Ti200 in legacy apps.

Keep in mind that in just "raw bandwidth", which tells absolutely nothing about the performance level the memory controllers can acheive, the 9700 only beats out the NV30 by about 4gb/sec. the shear efficency of NVidias memory controller is probably more than enough to make up the diffence in bandwidth. for reference, the Parhelia claims 17.6GB/sec, not that it gets them anywhere..

a well balanced and well designed architecture will perform quite well with a 128bit memory bus.

[Indiana]

O.K. so for you again, I wrote:

Expecially since even the 8x1 will likely be bandwidth limited

This is an assumption and the way the statement is written it should be pretty clear that it is an assumption.
Besides, anything that you, me or any other that does not actually have a NV30 prototype writes is only an assumption.

Still, even the R9700 with its massive bandwidth and its compression techniques tends to get bandwidth limited in 1600x1200 with 6x FSAA + 16x anisotropic filtering.

A 2TMU per pipe architecture does need MUCH more bandwidth than the R9700 can provide, so I'm quite sure that it wouldn't benefit the NV30.
Besides it is pretty damn hard to implement an efficient 2 TMU per pipe architecture with the DX9 pixelshader and this is probably the main reason why both, ATI and NVidia went for the 8x1 design. Those engineers are not plain stupid, neither at ATI, nor at NVidia, you know....