New 566MHz and 600MHz Celerons yet Coppermine Cores?

[MegaManX4]

It must be. Intel announced 566 and 600 MHz Celerons. But the max Multiplier is 8 and would max out at 533MHz with 66Mhz Bus Speed.
Or did Intel remaped some Multipliers to 9 and 10? or are they using a higher Bus Speed?
I thought the Coppermine Selerys (with 128k L2 cache) would be named as Celeron 2?

Who knows something?

Mega

[dZeus]

The new 'celerons' are being callen Coppermine-128's, and they have 128KB (not surprisingly) L2-cache. They are based on the Coppermine core, so they have SSE. THey run on a 66MHz bus. About the max. Multiplier of 8 o many BX-boards... I don't know what's up with that. Maybe they are meant to work only with Intel's 810e/820 stuff. But that would be really stupid of Intel is that is true, so I guess they just need a BIOS update or something.

[Maniac]

Me being a celeron fan,(pun intended I sure hope they will run on a BX platform. Somehow though I'm not sure Intel is going to play ball... 566 on a 66mhz bus should hit 850mhz or close to it. Who would buy the regular coppermine at 3 times the price?

Everyone's an overclocker nowadays right

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Celeron 366@567 2.2V, 128meg generic PC-100 RAM (running at CAS2) Abit BH6, G400 16meg DH@150/200, Western Digital Expert 18gig, Ricoh mp7040A(morphed to mp7060A) Pioneer 6X DVD slot load, Motorola Cable Modem w/DEC ethernet card, Soundblaster Live Value Ver. 2, Viewsonic GT 775

[shaqdaddy]

conspiracy theory: could intel be dumping coppermines that didn't quite make the grade and just releasing them as celerons?

shaqdaddy

[CrazyBee]

probbaly not dumped coppermines.. since, they have 256k cache and the celerons have 128K cache..

unless there is a jumper "somewhere" on the coppermine chip that can be modified. but, i sriosuly doubt it since I have seen one and there aint nothing to modify

[Thundrchez]

SRAMS (L2 cache, for example) nearly always have more memory than they are actually as listed as having...sortof. When you have a huge array of memory cells, it is not too uncommon for one memory cell to be bad. It is a shame to throw out an entire die because of just one chip.

Therefore, most sram manufacturers have redundant rows or columns of memory cells. You can blow fuses with a laser to disable the bad row/column, and other fuses to enable one of the redundant rows/columns. You cannot do this at home. This greatly improves the number of good die on a silicon wafer.

AMD had problems with their K6-3 with integrated L2 cache...they did not have enough redundancy to give good yield. Intel may be having the same problem with their coppermines, and hence introduce the coppermine-128. I dunno for sure...has anybody seen the die of a coppermine and coppermine 128 to see if they really are the same?

[Marshmallowman]

The new k6-2's(.18) from AMD are supposed to actually be K6-3's with one bank of there cache disabled
(AMD could not get high enough yields for both cache banks, so they just enable the good one, can be done via an instruction!!)

could this be happening with coppermines?, eg any CU-mines that have 2 good cache banks r slated has Cu-mines and ones that can't r thrown in the celery basket?.
Of course this would only be true if they have 2 cache banks, not one large one with redundant rows.

[MegaManX4]

The Coppermine 128 is indeed a normal coppermine with only half the cache enabled.
So say's the C't magazine (German).

Mega

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K6-3 400Mhz@450Mhz
G400 16MB, 192MB Ram and so on

[The PIT]

The best bit is that Intel are putting this chip against the Athlon. Whoops.