Why from 128bit to 64bit bus on g450 ?!?

[Marwyn]

Hm, I read white papers about G400,G450 and there is something crazy. On G400 is bus to videomemory 128bit long and on G450 only 64bit long. But WHY ?!? I thing, when G450 use 64bit bus, then must be slower then G400 (in texturmaping must be and higher RAMDAC dont help).

[HedsSpaz]

Because the bandwidth is the same! A 128bit SDR bus is EXACTLY(for practical purposes) the same as a 64bit DDR bus. I don't know why all of the reviews on various web sites haven't clued in to this fact yet, I geuss they're all just dense and not thinking.

At any rate, the G450 is slower than the G400 MAX, however it is ruffly the same speed as the standard G400. The point though is that it isn't slower.

[Marwyn]

Oh sorry, I mean G400 MAX of course !. Anyway why they use '64bit+DDR' and not '128bit+DDR'?!? I thing that '128bit+SDR' version is cheaper then what they use and have the same overal.

[HedsSpaz]

A 64bit bus is actually a fair bit cheaper to fab. A 128bit bus means(and I could be wrong on this) that there are 128 pins connecting the the RAM to the processor. On a 64bit bus there are only 64 pins needed. The result, is that the die size of the processor can be shrunk further, as well as the size and the number of layers on the PCB. Basically, it means less materials are needed to manufacture each card.

You are correct that SDRAM is cheaper that DDR SDRAM at the moment, but that won't be true for long.

Now, someone else expressed this theory once before, and I agree with them. The G450 is an experiment. Matrox just decided to do something useful with their experiment instead of letting all the money invested drip down the drain. M just wanted to prove that they could make a 64bit DDR bus that functioned on par with a 128bit SDR bus.

I have a theory that stems off of this. I think that the G800 will have a 128bit DDR bus.

So, just to clear things up, think of things this way.
(bits per transfer)*(transfers per clock cycle) = (net bits per clock cycle)

G400 == 128bits/1transfer * 1transfer/1clock cycle = 128bits/1clock cycle.
G450 == 64bits/1transfer * 2tranfers/1clock cylce = 128bits/1clock cycle.

G800 ?? 128bits/1transfer * 2transfers/1clock cycle = 256bits/1clock cycle?

Keep in mind that that is a completely wild and random geuss that seems to me to be the logical progression of technology.

[Targon]

It doesn't quite work that way. DDR allows for twice the data per cycle, so if you are using a 100MHz part with DDR technology, you are getting an effective 200MHz part. The problem is that with other cards going faster and faster, those of us with a G400 series card want something faster. Yes, 128 bit SDR is actually going to be slightly faster than 64 bit with a DDR added to it. It's why the 450 showed up as being a bit slower.

This is really the problem, many of us have been waiting a year or more for the upgrade to the G400, we get no news when it will come, and when something new comes out, it's something that's not even an upgrade, but running slower than what we have. A company like Matrox thrives on repeat customers, similar to high end car companies. A Porche dealership that didn't have old customers come back would find itself out of business in the long term. There may be new customers, but the bread and butter of a QUALITY product manufacturer is to get their old customers back. Those who had a G200 were willing to wait for the G400. Those who have a G400 are waiting for a G800. We havn't been told, so we wait. And in the process, Matrox loses the customers they could save by giving their loyal customers a hint about when the next generation cards can be expected.

In many cases, Matrox is lucky, nVidia based cards are really not revolutionary, they generally don't have anything to excite their customers. All they can do is boast high framerates for the same ancient first person shooters we have seen around for the past year+. Matrox is pushing for new features, such as bump mapping, but the lack of a customer advocate from them to get us excited and KEEP us excited is hurting them.

Where's the G800? What features will it have besides dual head and bump mapping? Is T&L officially going to be in there on the hardware layer? What other new features can we expect?

[Pace]

HedsSpaz was right Targon - it does work that way. Though you both do say that DDR provides twice the data per cycle.

So, an explanation from a trainee engineer:

A clock cycle is an electric pulse going hi-lo-hi-lo.

CLK: _|¯|_|¯|_|¯|_|¯|_|¯

A SDR memory bus will transmit data on either the falling edge ( ¯|_ ) or the rising edge ( _|¯ ). DDR transmits on both the falling and rising edge of the clock.

The same result is received however - half the bus width using DDR will give a full width SDR bandwidth.

The differences between 64 bit DDR and 128 bit DDR are minimal. The 64 DDR might get half it's transfer in half a cycle earlier or later. This is too time consuming to explain - and I might be wrong about this point so I won't bother!

Paul.

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[Gurney]

Just a little point about DDR.

Actually it uses two clock signals. A regular and so called differential clock. Basically the differential is a clock which is the mirror imaged of the other. The data transfers occur when the two clocks intersect. As below:


Take Care,
- James




[This message has been edited by Gurney (edited 20 September 2000).]

[Nick L]

wouldn't a 128bit bus have 128pins for data and 128 pins for addressing? (not to mention power supply)

[xortam]

No ... the number of data pins relates to the data bandwidth and the number of address pins relates to size of the address space.