Reactor Critical: G800 Cancelled

[superfly]

Exactly,just like GF1/2 and now 3,which internally are 256 bits but run on 128 bit memory bus(4x32 bit memory bus in the case of the GF3 though).

Btw has anyone seen the latest price drop of the GF3 because of the delays in getting the final revision of the chip to card makers???.

Of course Nvidia is saying that those price drops are happening because TSMC is already ramping up production of the chip,which i doubt very much.

It looks like elsa will be retailing their gladiac 920 boards for 399$ US once their available in late april/early may...

[frankymail]

Let me explain what I wrote:

by saying 2x 128 bits, I meant "2 bits per cycle per bit channel" (which means DDR). I know that DualBus is an Internal Read/Write optimization buzzword. I only said the G550 will have a 128 bits memory bus, sending 1 bit on both the rising and falling edges of the signal... Barb thought it would use a 256 bits memory bus, I said that it was incorrect, because it's a DDR 128bits bus...

Nevertheless, I'm anxiously waiting for the G550 to be announced What I want is an amazing 2D card with DualHead that will allow me to play DroneZ, Halo, Max Payne and Mafia when they ship, and that at good res and nice framerate, with every eye candies on...

Hoping for the best,
Francis Beausejour


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What was necessary was done yesterday;
We're currently working on the impossible;
For miracles, we ask for a 24 hours notice ...

[Barbarella]

If you want to take full advantage of 128 ddr, you have to use a 256 bits architecture.

If matrox do so. I doubt they will keep the internal dual bus architecture. But who knows ? O my god I just begun to speculate ... I don't want speculate anymore.

I WANT MY NEW CARD

[Barbarella]

"Barb thought it would use a 256 bits memory bus"

I never said this. Sorry for you.

[Ali]

Ah, I see what you mean now.

Actually they would only need 256 bit internal if they didnt have any buffer, which is quite unlikely.

With a buffer on the memory bus, say 128K to 1Mb you could bypass most of the timing issues you are thinking about.

Even the G200 had a buffer. I think it was 8K but I might be wrong about that.

Ali

[frankymail]

Sorry, I thought that's what you meant by
"if the next processor from Matrox use 128 bits DDR memory the processor will be a truth/full 256 bits." My fault

But having a 128-bits DDR memory bus do not requires a "truth/full" 256 bits design; a DualBus (two 128-bits Read or Write per cycle) bit design is more effective... That way, you can send AND receive data during the same cycle, where a "truth/full" 256 bits design would only allow to read OR write...

I don't mind how they do it, they could use babies' brains if they want (gross... ), as long as I can get a fast, trouble-free card with exceptionnal quality.

Francis,

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What was necessary was done yesterday;
We're currently working on the impossible;
For miracles, we ask for a 24 hours notice ...