Athena OC Program ... Where to Start...

[cbman]

Hi...

I finally got my Developers Password and the Documentation for the Athena Chip...

Inside it mentions that the VRAM is 80ns and also that there is a GCLK as well as VIDCLK and PCLK... As far as I can tell there is no MCLK... but that isn't going to throw me off...

Also it says that the GCLK has one Pin assigned to it... would that be a good place to start..

Just asking for some professional tips.



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Hang Low and Limber

[kjliew]

In the Athena block diagram, the GCLK is an input from a clock generator which determines the speed for Athena. VIDCLK is the input for pixel clock. PCLK is PCI clock which is probably driven from the bus. So potential overclock can be made by increasing GCLK. Athena uses external RAMDAC for analog output. Potential candidates for RAMDAC can be BT or TI. So, you need to find out who suppies the clock for GCLK, RAMDAC or CLKGEN. If CLKGEN, then software overclock is mostly likely not possible because Athena does not have software interface to CLKGEN. BTW, the type of RAMDAC may determine whether CLKGEN is needed. Modern RAMDACs have integrated PLL for clock signals. If GCLK is driven from RAMDAC, then software overclock is possible if the RAMDAC uses programmable PLL.

[cbman]

Thanks man.. I was guessing that I might have to start with something like that.. but I am glad to have some advice from an expert... Time to hit the books... and maybe print out some diagrams.

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Hang Low and Limber