What will we do if Parhelia doesn't make the shelves?

[Greebe]

FM, care to post up a cost breakdown per board when purchased in Q's of 100k parts of this hypothetical whammer jammer card with... uhmm lets say... 128 meg of DDR memory (if you want to use RDRAM or eDRAM include thos #'s too please)



PCB cost, mem cost (types used) etc etc etc

[Ant]

Do you work for nVidia? That is their usual tactic to get hold of Matrox development boards

Originally posted by frankymail

This raises an other question in my head: how much would you guys like to pay to get a engineering board? because if the price is right, I might consider breaking in and getting a few...

[frankymail]

Greebe: I'll do that first thing when I get home (I doubt my boss would like having me tdo that on the job

Ant: I am an engineer, but not for nVidia (or Matrox, ATI or Bitboys Oy ). I'm just a matrox fan since I bought an MGA Ultima for $700 USD

[Greebe]

ok will wait

[Wombat]

RDRAM is fast. VERY fast for bandwidth hungry processors.

But RDRAM is not something you want on vid cards. Latency sucks.

And on to franky...

I suggest you read my last post a second time...

I suggest you read other posts and who posted them.

Memory modules are used in serie, not in parallel.

It all depends on how you wire them. Could be either. Your ATI example was flawed because both memory configs were designed for the same data bus on the chip.

I hope you're nto attacking my profeciency, because that would be a mistake...

I will. Your "profeciency" and ego have you believing that everyone else's suggestions are impossible, even when some of us are dropping hints. Also, you slammed Nappe1 when he's 100% correct in his understanding of memory organization, and you are 100% wrong. A 256-bit bus can certainly be built using 2 128-bit chips. I'm glad you're not an engineer here. Your knowledge is forgivable, your attitude is not.

[Lemmin]

RDRam vs others

Hi, I'm not really technical enough, but I get the impression that RDRam is not suited to conventional graphics applications? (please correct me if I'm wrong).

Um, lets see if I can remember right - RDRam has a very very high throughput, but also a high latency? So its very suited when matched to the large pipeline of a pentium 4 of similar class processor, and means your system is absolutely stonking when crunching large amounts of data sequential (we use P4 Xeons here at work cos for compressing terabyte graphical images they are about 2 times the speed of Athlons, simply because of their long pipelines and the RDRam we put on them).

But as I understand it RDRam takes longer to access a given random point in memory than SDRam or DDR Ram etc (because of its serial nature)?

HOWEVER (wild alcohol-fueled speculation mode ON) what if we coupled say 8MB of embedded DRAM with 256MB of RDRam - the embedded memory would give us ultra fast chip-speed (single cycle) access times for geometry setup and texture effects, whilst the RDRam could stream in the raw textures as needed, and since a texture is (relatively) large the initial latency cost of the first seek would be offset against the faster transfer rate for the entire texture. This would allow a lower pin count (RDRam is specifically designed to have a lower pincount - serial vs parrallel). Would this then fit all the criteria? Fast internal 512bit bus for embedded ram, low pin count to external ram, and no hit on pin count because we are using RDRam instead of DDR? RDRam is surely cheaper than 128bit DDR, or QDR, or FCram?

As an even wilder suggestion, could we couple some embedded RAM with RDRam for texture storage, and DDR ram for frame buffer?

Please feel free to flame me with whats wrong with my assumptions - like I said I'm not good enough at interface architecture to see the flaws in the above.

LEM

[Wombat]

Addendum: If you want to get technical, only RDRAM runs in a serial setup. You don't run DRAM in "serial." If you take two DRAM chips and configure them together, you either double the address space (like on your Radeon example) or you double the data bus width (and the address lines would be wired exactly the same on both chips, assuming you don't mind taking the addressability hit, which is true 99.9% of the time)

[frankymail]

To Wombat:
Wow, i'm feeling like on a BBQ. I didn't flame anyone; why do you? My Example of the Radeons for Nappe1 was OK, because it's the way most single graphic chip boards are made (and the counter-example was easy to express). Also, I know that it's possible to make a 256 bits bus using two 128bits chips (or two series of chips) in "parrallel" (multi-channels) (BTW, Nappe himself used the example of the Radeons saying that it had 4 32 bits buses...). Dual-channel memory architechture is already used my Intel i850, i860 & i870 chipets, as well as nVidia's nForce. The point was that doing so (dual 128 bits channels) adds more than 150 pins to a graphic chip with a single 128 bits memory bus, which is something you don't want. More pins means more traces, bigger PCBs and maybe more layers... more costs.

Also, Nappe was refering to the use of 256 bits DDR memory chips: I was just telling that it would be very expensive and that also these chips are not available. And since when are you dropping hints about Matrox' new products? Do you work for matrox? (if yes, you have a lot of travelling to do each morning ) Do you know anyone there? Did you see a Parhelia working sample in action? I work for a corporation that is a big client of MGA division, but given the fact that I don't get a lot of info from them, I only give my oppinions, and I don't say otherwise.

About my Ego/Attitude or whatever you call it (here we call that character ), I didn't want to be offensive to anyone. If, by mistake, I did, believe me, it wasn't intentional, and I'm sorry about it. But, I never said anything proposed here was impossible; I said it was unprobable due to certain constraints. I always take time to consider thouroughly others ideas. Also, I tried to correct things that, to my knowlegde, are wrong. I might have done some mistake myself, I don't deny it, but I'm able to acknowledge it (I don't immediatly go to DEFCOM 1 about it ). Besides, Isn't the purpose of life to make mistake, learn from them and do better next time? Perhaps I'm wrong believing that Parhelia will have on-die or embedded RAM and 128 bits DDR memory chips and will not use 256 bits DDR memory chips, perhaps I'm right. Anyway, everything will be crystal clear in may/june, right ?

I'm no bad guy, and I'm sure none of you are either...

C Ya later (I haven't forgotten you Greebe

[bjb]

Hi everyone,

wow, 1st post .. hope not to offend anyone, but I couldn't resist

frankymail, getting back to what you said about memory-bus design I would like to add that I belive that you're not entirely correct here either. You state that memory-bus design is alway serial, which is not correct. A short example: A 32 MB Radeon uses 4x 32 Bit DDR rams that run what you call "in parallel". The 64 Meg version uses 8 32 Bit DDRs where the organisation is 4x2 . There are 2 CS (Chip Select - not getting deeper into RAS/CAS) traces to both banks. A "serial" bus would mean you had 8x 128 Bit chips but that is even more inefficient as you would need 8 CS traces instead of 2 (ie more pincount with 128 bit DDRs than with 32 Bit). And 4x32 doesn't necessarily mean "multi"- bus design. You can still use the very same CS/CAS/RAS traces for all of the 4 chips in a single "bank".
Anyway, from a design point of view, memory buses are "always" (except for example Rambus) "parallel" designs even when using multiple chips in multiple banks.

So I believe what nappe1 said is right and a 256 bit Bus does neither require 256 Bit DDR chips nor multi-bus design (even though I belive P. will use multiple independent buses). The fact that remains true is that this will cause the pincount to jump quite dramatically, unless they use a multiplexed bus with demultiplexers in front of the ram.


cheers .. Bjoern

[frankymail]

Hey, you have to take the "Serial" in context here (I do know that usual DRAM isn't a serial architechture, and that RDRAM is the only serial memory out there, and that is why you have to "terminate" (you see I'm using quotes so people don'T think the terminators are actually used to kill the memory modules ) the channel using a terninator. I just wanted to show him easily that is not using 4 32 bits channel but one 128 bits memory bus). BTW, Nappe said he thought Parhelia will use 256 bits DDR chips, not a 256 bits memory bus...

BTW, don'T mind getting technical: it's a forum, so anyone who doesn'T want to doesn't have to read it, but those who do can learn something


Edit: Please don't start with the multiplexing !!! Thats is the thing I hated the most to learn when I was attending UdeS

[Ant]

Quite right!

Originally posted by frankymail

BTW, don'T mind getting technical: it's a forum, so anyone who doesn'T want to doesn't have to read it, but those who do can learn something

[bjb]

fm, well than I should've read more carefully anyway ... agreed !

cheers .. Bjoern

[Parhelia Pro256]

Interesting.... by taking all of the info in the last say; 20 posts, you have the design of past, present and future samples

[Lemmin]

MURC graphics chip?

Hehe... if we carry on in this vein for another few days, we'll have designed our own MURC graphics chip...

Maybe we should set up a little company, since we seem to have a management structure (Haig for president!) some PR people to do press releases, marketting people to design boxes, and now some chip architecture people to design us a product.

In fact, haven't we got everything the bitboys have, and more?

Lets call it the MURC Rumour 1024 Pro and see if we can get some investors!

LEM

[Wombat]

Do you know anyone there?

Yup, most certainly do. I'm a BB, and probably have more info than Ant