DX 9 Possible on .15micron?

[Ali]

According to this slide, the R300, which is a DX9 part is going to be made on .15 micron process.

That means it is possible to do.

This suggest to me that either the R300 is going to be huge (bigger even than the Parhelia), or they have found a way to implement PS2.0 and VS2.0 using less transisters than anybody else.

I wonder what this means for the Parhelia?

Ali

[ALBPM]

A few of us tried to tell you guys that .13u isn't that critical, eh Wombat

Paul

[rugger]

Another set of us tried to tell you guys that Direct X 9 didn't matter either, but.....

[Wombat]

Yeah, it's amazing what you can do with "old" processes.

Nobody ever said that you can/can't do DX9 on a 150 process.

That's like saying, "My Eclipse is turbo-charged, and that Ferrari isn't. I must be better."

[rugger]

Well, the shrink from 0.15um to 0.13um only reduces the size of a chip by 25%.

Not the massive improvement some think

For CPU manufacturers however, a die shrink from 0.18um to 0.13um will reduce chip size by about 50%, a much bigger improvement.

[Wombat]

25% is a massive improvement. All other things being equal, I certainly wouldn't mind it. First order, the way fab defects are distributed, the odds of a die having a failure goes up exponentially with area, so yields plummet as the die size grows. Also, if you decrease die size by X, then the average distance for signal propagation decreases by 1.4X, so critical paths speed up nicely.

Of course, what Paul and I have been saying is that right now, with 130nm, those "other things" certainly aren't equal.

[rugger]

Originally posted by Wombat
25% is a massive improvement. All other things being equal, I certainly wouldn't mind it. First order, the way fab defects are distributed, the odds of a die having a failure goes up exponentially with area, so yields plummet as the die size grows. Also, if you decrease die size by X, then the average distance for signal propagation decreases by 1.4X, so critical paths speed up nicely.

Of course, what Paul and I have been saying is that right now, with 130nm, those "other things" certainly aren't equal.

Of course it is a nice improvement. But it isn't the sort of improvement people here on the boards have been hyping it as.

[Wombat]

Sure it is. Going from a mature 150nm setup to a mature 130nm setup is a very nice improvement, 30-40% speed boost under ideal conditions. The problem is, there are no mature 130nm fabs, and won't be for some time.

[Tempest]

Yep, the fact that they say the R300 has been sampling to partners for some time makes me think that 0.15 is possible. But that is an old roadmap (notice it was done before the R200) so things may have changed since then.

[Novdid]

A few samples is a whole another thing than massproducing for the retail or OEM market.

[Wombat]

There are only a few places that might be doing 130nm:

1) AMD - and from the T-bred pushback and previews, they don't seem to have it down yet.
2) Intel - but they don't share the fab
3) TSMC - they aren't ready
4) IBM - IBM has lower standards for "ready" than you would like
5) Samsung(?) - I don't know if they have it yet, but they will eventually need it.

[ALBPM]

Piece of Cake!!!

But we don't share.......BWAHAHAHAHA!!!!!!!!

Paul

[dneal]

I think the issue with Parhelia was the Matrox wanted to put so much other stuff on there that DX9 took a back seat. Not too bad really since DX8 is still not really taken advantage of.

[Kosh Naranek]

Originally posted by ALBPM
Piece of Cake!!!

But we don't share.......BWAHAHAHAHA!!!!!!!!

Paul

Correct me if I'm wrong .. but Intel is actually implementing/producing with 0.13um CU rev. 2 on 300 mm wafers .. right ?

So why not give Matrox some of that 300 mm capacity ?

[Wombat]

Because Intel doesn't share their capacity. They always keep their fabs full with their own stuff.