Help!

[3dfx]

I'm doing some homework :P

An example of a situation where static memory would be used as opposed to dynamic memory is ??

[TransformX]

You mean SRAM vs. DRAM ?
SRAM costs more but takes less current and is much faster. Thus it's mostly used as on-die cash.

For more info and examples, try http://www.google.com/search?hl=en&i...q=sram+vs+dram

[3dfx]

Thanks for that info

[Marshmallowman]

dram uses less transistors per bit, but each bit must be refreshed ever x nanseconds or so.

sram is does not require refreshing but does use quite a few more transitors per bit....there are quite a few memory tech that are in between the two, but usualy get classed as one of the other due to there relative perfomance.

sram was often uses for persistant memory in some device due to not requireing memory refreshes, but since modern dram is very energy effiecnt this is not really the case anymore,

eg dram is cheaper to make , but sram has performance to justify its price. Also memory densities of dram are a lot higher for the above reasons

sdram is just synchonus dram , I think the main imporvemnt is that memory access cycles can overlap for better performance...It is of course the must commonly used stuff in computers now days (well ddr versions anyway)

[Jammrock]

SRAM is used in devices such as MP3 players and PDA's. Flash RAM is a type of SRAM. SRAM allows you to remove the media from an MP3 player, plug it into a card reader on a computer without losing the data in the memory while there is not power running to it. Easiest example to use.

Jammrock

[spadnos]

Originally posted by Jammrock
SRAM is used in devices such as MP3 players and PDA's. Flash RAM is a type of SRAM. SRAM allows you to remove the media from an MP3 player, plug it into a card reader on a computer without losing the data in the memory while there is not power running to it. Easiest example to use.

Jammrock

Unfortunately, it's an incorrect example.

SRAM is just as volatile as DRAM - it goes away when power is removed. You may be thinking of Flash memory, which is non-volatile.

SRAM has a larger cell on a chip die, and so is more expensive. DRAM is a small and efficient design, but requires extra external logic to keep it refreshed - something which most small microcontrollers don't have. SRAM is also a bit faster (clock for clock) than DRAM (I don't remember the exact timing reasons, I just remember that it's true ).

SDRAM is just "synchronous DRAM" - the CPU and memory share the same clock source. That means that certain "attention" signals don't need to be used, which saves time. Synchronous operation also allows for better burst operation (the 4-2-2-2 that you used to see for memory timing - "4 clocks for the first access, then 2 clocks for each of the next 3 in the burst")

- Steve

edit: of course you're thinking of flash - you said so

[Umfriend]

I thought DRAM essentially uses leaky capacitators (that need to be refreshed as they leak = lose their status) while SRAM were sort of magnetic switches that maintain their status (North or South e.g.) for a long long time??

[Jammrock]

SRAM = STATIC RAM. You are thinking consumer jargon SRAM (synchronous), not true SRAM (Static).

http://www.pcguide.com/ref/ram/typesSRAM-c.html

You were correct about the volitility part SRAM is much faster and more reliable than DRAM, but more expensive. BIOS's commonly use SRAM, thus the need for a CMOS battery. As long as there is power to the SRAM, it keeps it's state (memory).

I guess I'm a bit rusty on non-DDR RAM's

Jammrock

[spadnos]

Originally posted by Umfriend
I thought DRAM essentially uses leaky capacitators (that need to be refreshed as they leak = lose their status) while SRAM were sort of magnetic switches that maintain their status (North or South e.g.) for a long long time??

I think you're thinking of bubble memory .

DRAM does use leaky capacitors, while SRAM doesn't. It's not a magnetic thing, though.

(rummages around on the net):
I found out why SRAM is faster - it's direct access. An SRAM chip is generally configured as a one-dimensional array of words (a word generally being 8, 9, 16, 18, 32, or 36 bits). You only need one chip (assuming you use the correct width for your system) to implement the memory subsystem. The chip has enough address lines to be able to select any word location on the chip (so, 16 pins for a 64k chip, 18 pins for 256k, etc.). So an access cycle goes like this: Set address on address pins, wait, assert read/write pin, wait, read data.

A DRAM chip is usually one or 4 bits wide (so you use multiples to get the correct word width), and is arranged in a 2-d array. This has the advantage of using less pins (half the address pins, since each pin does double duty as a row and a column address), at the expense of extra time every read/write operation: Select column, wait, select row, wait, assert read or write pin, wait, read data - note the extra "set address / wait" in there.

Isn't engineering fun?

- Steve

[3dfx]

Thanks ppl