Parhelia 2: Late 2002?! (compl. DX9; 0,13µ)

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  • borat
    Super MURCer
    • Jul 2001
    • 1035

    #16
    the origional idea was that it would move to 0.09 micron in summer next year however given the poor take up of the card i suppose it is possible that they have decided that in order to survive they need a faster part now as unless they do they will get very little revenue between now and the next release, matrox could go under with parhelia if sales dont pick up as it must have cost a bomb to develope. as for ddr II there is no need for it it is the clockspeed of the chip which lets it down some sort of bandwith saving may be an economical way of making the most of the 256 bit ddr though
    is a flower best picked in it's prime or greater withered away by time?
    Talk about a dream, try to make it real.

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    • Chrono_Wanderer
      Super MURCer
      • Mar 2002
      • 2540

      #17
      yea i think matrox should up the clock and fix up the Anisotropic filtering/or other serious issues first to build a good repetition of the chip. They should finish up the rest of the DX9 specs before moving to DDRII.

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      • Fluff
        Super MURCer
        • Apr 2002
        • 1522

        #18
        I personally think that DDRII must be easy to implement as thay have a memory controller section on the chip. Fixing FAA is probably much harder as it has to work in all games, (all the ways that developers choose to creat emodels and scenes.
        ______________________________
        Nothing is impossible, some things are just unlikely.

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        • TdB
          Super MURCer
          • Jan 2001
          • 1238

          #19
          IS anisotropic filtering broken, or is it just a driver issue?
          This sig is a shameless atempt to make my post look bigger.

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          • Slougi
            MURCer
            • Feb 2002
            • 368

            #20
            Originally posted by Fluff
            I personally think that DDRII must be easy to implement as thay have a memory controller section on the chip.
            What's your point here? ALL chips have a memory controller.
            IS anisotropic filtering broken, or is it just a driver issue?
            This is just a hunch, but i'd say driver issue.
            -Slougi

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            • Fluff
              Super MURCer
              • Apr 2002
              • 1522

              #21
              I'm implying that DDRII is probably quite easy to implement at a chip level. And changing the structure of pipelines/algorithms etc is much harder as from my point of view a memory interface is pre-defined.
              ______________________________
              Nothing is impossible, some things are just unlikely.

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              • Chrono_Wanderer
                Super MURCer
                • Mar 2002
                • 2540

                #22
                boy this thread is dead boring comparing to the time when P was being launched.... anyways...

                how about 256-bit QDRII-eGRAM

                edit: typos

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                • Novdid
                  Super MURCer
                  • Nov 2000
                  • 2609

                  #23
                  Originally posted by Chrono_Wanderer
                  256-bit QDRII-eGRAM
                  Aren't these typos??? Oh well...

                  Comment

                  • Chrono_Wanderer
                    Super MURCer
                    • Mar 2002
                    • 2540

                    #24
                    Originally posted by Novdid


                    Aren't these typos??? Oh well...
                    Yes it was a typo. I actually meant 1024-bit QDRIV-eGRAM

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