Some More P4 Action!

[TdB]

personally, im hoping for a clockless bus, that will be the best thing to do, but i´m not sure it can be done while staying copatible to existent hardware, since it will require that each hardware has a clock of there own.

[Wombat]

Clockless bus! ROFLMAOSHIPMP!

[Novdid]

Can you run that by me again Wombat.

[Greebe]

Must be related to ROFLMAOATPMP

[Technoid]

FSB speed!

I totally disagree with your straw theory !!!! Which the recent developments in RAM speed and bandwidth does too.

A picture says more than a thousand words

[Wombat]

And what that picture says is that the Hammer should have been designed with a 128bit data bus. Not faster man, wider.

Something is wrong with that picture anyway. Where's the chipset? Did they put the MTU and all its buddies on die? I hope not. We pull it off on the PA-RISC processors, but I don't think AMD can or would want to do it here.

[Technoid]

And I say Again LOOK at the picture!

Se those big gren squares with the name AMD-8151 and AMD-8111?

Thats the south and north bridge!!

Also;

The AGP has 32bits at 533Mhz

Hypertransport Don't seem to have a fixed "width"!
It has a multiple of 2 -->32bit "Links" that can be simultaneously used in either synchronous mode or isochronus!

Chew on that!

[Greebe]

I was reading an article late late lastnight which showed the difference between dual XP/MP cpu and dual Xeons with and without Hyperthreading (can't find the link atm but I'm still looking.. thought it was on 2cpu.com but...).

Basically with Hyperthreading enabled using Sissoft Sadra (the only app which has Hyperthreading optimized code atm) the Xeons lost ~15% (off the top of my head) performance vs the same system with it turned off!

Not only that but since Hyperthreading requires the code to be modified inorder to be utilized.

All in all the conclusion basically gave Hyperthreading a poor score. Not only that but the consensus of programmers concidering implementing this was low... they just didn't like it at all.

Guess that's something else to chew on

[Wombat]

And I say Again LOOK at the picture!

Se those big gren squares with the name AMD-8151 and AMD-8111?

Thats the south and north bridge!!

Look at your own damn picture. See the "north bridge"? See how the RAM is NOT connected to the north bridge? That's my problem. They have the Hammer acting as the memory controller. No way they're that dumb. I really hope a chip is missing there, or a line is drawn the wrong way. After all, why have all that throughput to what's basically your peripheral controller? Also, if this is supposed to be a server, where's the other cell interconnects?

Still, it shows a 64-bit data bus to the RAM, which runs on a bus no faster than what you can get today. It's been publically released that McKinley has a 128-bit data bus, and it was a <I>damn</I> smart move. Hammer will be hurt because it doesn't have that.

Also;

The AGP has 32bits at 533Mhz

So? Are you trying to make a point here, b/c it's not working. The picture doesn't even mention which part of the AGP 3.0 spec it's following, since they all have a 66MHz clock (with quad or octal data transmission). For those in the audience who care, I glanced at the spec. Dropped to a .8V signalling level, inverted lots of signals, and has a synchronization routine.

Hypertransport Don't seem to have a fixed "width"!
It has a multiple of 2 -->32bit "Links" that can be simultaneously used in either synchronous mode or isochronus!

Once again, you're tangling without a point? What are you trying to say here? Yes, HyperTransport is cool. It seems to be a damn fine implementation of point-to-point low-voltage differential signalling. And look, when they need more bandwidth, they widen the data link. And it's not a bus, it's a PtP. A controller is going to need separate lines for everybody.

Chew on that!

Hmmm? Sorry, not a lot of substance to chew on. Don't know why you're all riled up though.

(fixed open bracket)

[Marshmallowman]

claw hammer has its own ddr memory controller built in (single channel)

(sledge)Hammer will have two ddr memory controllers (dual channel)

by having separate memory controllers and hypertransport they have effectively opened that the fsb bottleneck by a big chunk

claw will have two hyper transport links...
sledge will have four hyper transport links..

sounds Fecking good to me

[Wombat]

So, I've been checking this out: http://www.amd.com/us-en/assets/cont...esentation.PDF

Interesting design decisions, not sure if I'm a big fan of them. The memory controller on the CPU has a lot of implications:
Can they do it right?
No upgrading the units separately
The area cost of memory controllers
binding two units you used to OC separately
Theoretically cheaper MBs, since they don't have to have a north bridge on them.
CPUs have to be from matched lots now?
How the hell are they going to chipkill with this setup?
Losing a CPU means losing the memory it was controlling?

Some of those combos don't thrill me either. MP systems have the path from device to memory going through 2 CPUs or more. CPU-to-CPU could take 3 hops in an 8 way.


Tons and tons of other stuff. I could spend an entire afternoon debating it. It all depends on how well they execute, but they've taken a big risk here. All in all, I say icky, nasty. Even if it performs, I have serious concerns about system reliability.

[KvHagedorn]

icky? nasty? Well, it's hypertransport. It's a revolutionary way of doing things. We've known about this for months now. I would think that having the northbridge built in would be a rather elegant solution. You eliminate one more thing being limited by fsb speeds. Now you understand why Sledge is on a 940 pin socket and claw is on a 754 pin.

This is all rather new but a step in the evolution of the thing. One day, EVERYTHING will be on one die. Remember math coprocessors? Slick when they integrated them onto the chip, wasn't it? Next came L2 Cache, now the northbridge too. Next will be RAM!

[KvHagedorn]

Oh, in case you guys wanna see the page with the sockets.. it's here

[KvHagedorn]

Oh, and the 8151 is the HyperTransport AGP 3.0 Graphics tunnel (just talks to the AGP slot).. The 8111 is the Hypertransport I/O hub (southbridge). There is also a 8131 which is the PCI-X tunnel (on the server chipset.. super PCI interface)



The chipset pic Technoid posted was only for clawhammer.. Marshmallowman is correct.. moving up to Sledgehammer gets you the 128 bit wide data bus.

[Wombat]

Oh, well LDT is cool, I never argued that. But putting the memory unit on the die like that is risky.
This isn't like adding the x87 unit.

Adding the x87 to the die is like having a TV that doesn't need a cable box. Adding the MTU is like owning one of those TV/VCR combos. Oh, and then try to sell it for mission-critical applications.

Why not have a LDT link from the CPU to a north bridge chip? You could use the die space for more cache.