Some More P4 Action!

[Marshmallowman]

would you rather have via make the memory controller.?

I think its a good idea.. there reference design is a 4 layer board... (not 6)
The integration of the memory controller is going to payoff in reduced motherboard complexity and performance since there will be no intemediate chip(and traces) causeing timeing/latency problems.

and with the agp 8x bus/IO and memory connected INDEPENDENTLY to the CPU it will fly.

But you are right about loosing access to half your memory if processor dies(1 in 100000?) in a dual cpu setup, but you do get it back when you replace it also you don't get both CPU's fighting over memory bandwdith as much.
I want 1

[Wombat]

would you rather have via make the memory controller.?

How about anybody, making any other memory controller? Now you can't use the same CPU on an updated system, b/c the update would go with the CPU. AMD did a nice job with the 750 and 760 chipsets, I don't know why they couldn't continue.

I think its a good idea.. there reference design is a 4 layer board... (not 6)
The integration of the memory controller is going to payoff in reduced motherboard complexity and performance since there will be no intemediate chip(and traces) causeing timing/latency problems.

I kind of expected a 4 layer board anyway. LDT does offer that lower pin count.
Yes, from a theoretical performance standpoint it does seem nicer. But is it worth it? So many real-life complexities, and reliability/redundancy problems.

and with the agp 8x bus/IO and memory connected INDEPENDENTLY to the CPU it will fly.

No, this is no different than having an off-die north bridge. Except that now things like DMA transfer have the CPU more closely bound: a bad idea if you're pushing the performance edge. The last thing these guys need is more heat for their die.

But you are right about loosing access to half your memory if processor dies(1 in 100000?) in a dual cpu setup, but you do get it back when you replace it:

More like 1 in 1000. Or 2, for 2 CPUs. So, 1 in 500. Even worse if you're in an 8-way box. Not the kind of odds that I want in my racks. Also, if you lose a CPU, I hope that the rest of the system will re-route around it. Even still, you will lose the data in that RAM array, and no other processor will be able to pick it up. Now, if two processors happened to be sharing memory when the one controlling that address space goes belly up, you're screwed.

also you don't get both CPU's fighting over memory bandwdith as much.

Assuming that they're doing 8 independent jobs, with no memory sharing, and adequate RAM in their own bank.
1. There's plenty of other ways to do that. Why not just have a separate north bridge, and an LDT connection to that?
2. What about all the situations where memory is not under a certain processor's control?

Also, how cell-organizible is all of this stuff? If I have an 8-way box, am I limited to them only running as one 8 processor system? No partitioning? What if I have to reboot one processor, will its RAM still be accessible to me?

I've been working on a good bit of MP stuff at work lately, and this really just gives me the creeps. My first instinct is that this reduction in latency isn't as much as a boost as cache would be, esp. if you did something like a north bridge with an LDT connection and L3/L4 cache on it.

[Marshmallowman]

I noticed that in a 2 CPU config, that the 2nd cpu is only connected to the first and not to the io stuff..etc. It might be that if you loose your first CPU the 2nd CPU cannot function?..

hmm...I think I wait for an independent preview/review to make any kind of judgement.