Parhelia needs .13 micron

[KvHagedorn]

Alright, to return to the topic at hand.. putting Parhelia on a .13 micron process will not in itself solve the speed problems. There are many more factors than just the size of the traces (and, as I said before.. there's not really that much difference between .15 and .13.) Hardware revisions could easily get this card above 300MHz on the .15 process with adequate cooling, but Matrox is constrained by the AGP spec, so you can't have huge heatsinks like you can for CPUs. This might change as things progress though. Back in the day even CPUs had no heatsinks.. more recently, memory controllers and video chips did not need them. Now if you get a Gforce Ti4600, you wind up with heatsinks on chip and memory, and what looks like a turbine over the chip. We are obviously at a point where the AGP spec has to be revised for higher performance cards. Most of us do not use the PCI slot next to our video card anyhow, unless we absolutely must. When I get my P, I'm probably going to OC the hell out of it as soon as there is a proven utility out there. I'll add a huge copper heatsink and fan and put heatsinks on the memory chips and go as high as I can with it.

[Goc]

Same here! I think I could even spare first two PCI slots...

From what I read, this baby simply screams for overclocking!

[Snake-Eyes]

Originally posted by KvHagedorn
When I get my P, I'm probably going to OC the hell out of it as soon as there is a proven utility out there. I'll add a huge copper heatsink and fan and put heatsinks on the memory chips and go as high as I can with it.

Please post the results here. I really want to see how the P could have been out of the box. Who knows, I may still end up with one, if it turns out to be a screamer..

[William]

OK, I realise that it is probably going to get very warm around here after me posting this, but Tridet Micro seem to believe that their new graphics chip (the XP4) is going to be produced by UMC on a .13 process, and they had engineering samples shipping a month or so back. I thought UMC didn't have a (commercialy viable) .13 micron process yet?

The big difference between this & Parhelia seems to be that the XP4 is "only" 30 million transistors. Hopefully someone can explain to me where my logic falls down...

[ALBPM]

Now, I believe that it's TSMC that doesn't have the 0.13u down yet not UMC.

Reference this thread:
NV30

Paul

[William]

I thought this thread was establishing that Parhelia wasn't fabbed at .13 micron because UMC couldn't do it acceptably.

<...goes back through the thread...>

[Wombat]

No, not at all. P was planned as a 150nm part.

[William]

OK thanks; I'm gald I've cleared this up in my mind now.

[[Ch]amsalot]

Wombat,

I'm curious as to how NVIDIA can clock its .15 micron NV25 (GF 4 Ti) to such speeds as 300MHz but the Parhelia is limited to 220MHz.

I would think that the larger die size of Parhelia would enable better heat dissipation.

Is it all a matter of pipeline?

-[Ch]amsalot

[Wombat]

I'm curious as to how NVIDIA can clock its .15 micron NV25 (GF 4 Ti) to such speeds as 300MHz but the Parhelia is limited to 220MHz.

Clock speeds don't mean much. I don't know either of these architectures, but it may be that P does more per clock. It's like comparing a P4 to an Athlon more MHz is useless if you do less per clock.
Most people tend to treat MHz like horsepower, when it's a lot better to think of it like rpm's. You have your big blocks, with low rpms but a lot of push, and you have your S2000s, which only go fast when they hit 8000 rpms or so.

Larger dies are bad for heat dissipation. First off, Silicon isn't the material of choice for heat dissipation. Secondly, the die <I>creates</I> the heat you want to dissipate, since the only reason you would have an area of silicon is to have circuitry on it. If you look at CPU design, you'll see that the hottest units are placed on the edge of the die (like FPUs). This is so that they contaminate less of the die with their heat - the heat radiates in all directions, and if you're on the edge of the die, you'll dissipate into the packaging.

[Greebe]

Chams, some of what you're asking is beyond what those in the know can discuss... ie NDA

Now if you understand IC design, then I'd suppose you would already realise that there is much more to what causes a clock limitation than say bus width or thermal issues. There are fab issues, design issues, what comprises the seperate sections of an IC especially in today's programmable GPU's and packaging issues which all manufactures deal with.

This is no different than memory controllers ineffeciencies which even ATI/nVidia has problems with. Tho this one is a non issue with Parhelia.

[[Ch]amsalot]

Wombat & Greebe,

Thanks for the replies guys.

-[Ch]ams

[Sandog]

KvHagedorn

Your a wise man.

[Rags]

Originally posted by Sandog
KvHagedorn

Your a wise man.

No. He's a Wise ASS and he knows it.









Rags

[xortam]

Drop it MikeHolli ... you're not helping anybody. The issue is over and everyone's moved on.