Serial ATA Beginning to Appear

[Marshmallowman]

Gurm I never said serial ATA would do more than 1 drive, which is good since we should end up seeing 4 serial ATA ports on MOBO's as standard eventually(so I will never be in the situation where I am forced to share a channel)

I have 3 HDD's on separate channels, and my DVD and CD/RW sharing the other channel.

So I want to add another HDD, how can I add another HDD and still maintain the current performance levels.(without getting another controller)

It can't be done because the perfomance limitations of the 2 drives on an a single channel.

I do know that there is no drive currently available IDE hdd that will come close to maxing out ATA100 let alone ATA133(except maybe some exotic solid state drives)

Edit: to add, 64bit PCI and 66Mhz PCI are not too uncommon anymore 100MBps is close the limt for "old" PCI tech, you can at least double that for people with dual athlon boards...etc

[DGhost]

SATA currently does not support more than one driver per port. that is something intel is planning on implementing in SATA 2.0

that being said, i could see SATA offering an improvement over ATA with multiple SATA native drives attached, due to the smaller amount of data its moving per cycle. finer grained transfers when dealing with multiple transfers at once should improve transfer rates, especially since thats really the problem with normal ATA - it is just not fine grained enough for multiple high speed transfers.

only problem is it does not really seem to address any of the short comings of IDE except for the cables.

Marshmallowman, the problem is that all the boards with 66mhz/64bit PCI slots are horribly expensive. plus, it takes devices that support it to use it. this does not really fix the underlying problem... plus, even with the 760MPX it is still sharing a single relatively low bandwidth bus to all of those...

a more effective solution would be to offer each 33mhz/32bit (or even 66mhz/32bit) pci slot its own dedicated 133mb/sec bandwidth to work with. some of the high end intel server boards have multiple PCI buses to ease the situation with them.

Edit: finishing thoughts... problem with doing that is that it requires multiple PCI bus implementations in the southbridge, a much larger connection between the northbridge and the southbridge, and several other things that would drive motherboard cost through the roof.

the AMD Hammer architecture provides a platform where bandwidth is highly scalable all the way down to the PCI buses in MP configurations. it will be interesting to see the Quad processor boards and what they introduce as far as I/O options...

[Marshmallowman]

good point, I don't think I will be getting a 66mhz 64bit pci mobo any time soon, and then there is the cost of the 64/66 PCI cards themselves.

[The PIT]

Just wait until we get solid state storage devices then matters will speed up.

[Dr Mordrid]

Not so.

The RT.X100 can be made to push 90-100 mb/s through the PCI bus when doing complex realtime stacks, especially if this is combined with realtime timeline export to HDD or IEEE-1394 .

This is why it cannot use the VIA chipsets, which max out at <90 mb/s. Put the RT.X100 on a VIA chipped board and realtime export functions, among other things, go straight to hell regardless of where the drive or array is attached.

The end result is the same on KT266 and KT333 chipsets, so how each is screwing up is more a historical concern than anything else. Either way they suck.

OTOH the SiS 6xx, 7xx and Intel 845E chipsets handle the same stacks just fine, which means they must be capable of >100 mb/s to be able to do this plus handle the system overhead.

Dr. Mordrid

[WayneHu]

It is not kind of easy to implement the multi-channel PCI buses.

1. The chipset pin-count increases.
2. The chipset has to provide large read/write buffers to get the best utilization.
3. When the buffer depth is high, the collision detection logic is even more complex.

VIA / Sis / ALi always claim their superior bandwidth architecture. In reality, they did not do or finish the full validation of it when the product enters the market... One of my friend tried to implement a PCI feature with VIA chipset on his project. After wasting three months to investigate the correctness of that certain function on VIA's south bridge chip, his team found out that VIA does not totally follow the PCI spec to design their chipset. As a result, the company gave up that project on VIA chipset.

It is sad that there is no good and almost bug-free product like the old day Celeron(Mendocino) + BX chipset with good price tag. Currently the more acceptable one is P4-1.6A + i845D combination although it is not as scalable as other vendor's chipsets and the CPU's performance is so so. At least its implementation and timing design on each bus protocol are validated and running quite stable for the long term usage. Basically, I do not trust those chipsets that need a fan to cool it down especially when most vendors do not attach a good noiseless fan on it which is for the long term use.