Rumour: G400 already T&L capable ??

[Azagal]

Hey Stil, these 32mb of memory ain't enough for you? If they aren't enough you have the system memory avaible through the AGP. And one more thing, the register are not to store data from frame to frame, no processor has registers to store a whole frame or the data for it. If you don't know the Pentium and all other 80x86 processors has only one 32bit register designed to store date, you can get 2 if you don't use for their purpose.
And for integer calculations, there is no problem using FP registers for that.

[Azagal]

Hey Stil, these 32mb of memory ain't enough for you? If they aren't enough you have the system memory avaible through the AGP. And one more thing, the register are not to store data from frame to frame, no processor has registers to store a whole frame or the data for it. If you don't know the Pentium and all other 80x86 processors has only one 32bit register designed to store data, you can get 2 if you don't use for their purpose.
And for integer calculations, there is no problem using FP registers for that.

[Gavin]

That's what happens when one posts rumours from other sites:

This morning, I had 22 replies in my postbox in Outlook ;-) ;-)

I Better uncheck the "reply by mail" feature in the future :-)

[Unam]

I know that Matrox built the G series to be extensible, but really people the microcode required to do T&L in hardware is significant. I'm willing to bet that the reason Matrox is not saying anything about T&L in hardware on the G series is that there will have to be some changes to the basic Warp engine. Thus the G450... if your going to go to a new fab you might as well make all your changes at once! The G series may indeed be capable of hardware T&L but not without a HUGE performance hit, again we can see why a G450 would make sense and also why Matrox would not say anything about the exisitng G series being capable of hardware T&L.

My two bits...

BTW, Ant what do you have to do to be a MAXIMurcer?

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Asus P3B-F1, PIII 600B, 128Mb PC133 RAM, 18.2 KA drive, HP CDRW & Travan drive, SB64PCI, Intel EPro+ PnP NIC, G400.


[This message has been edited by Unam (edited 17 December 1999).]

[Borg]

uaaaaaahhhhh !......you guys should work for MATROX...seams thet matrox doesnt know so much about their chip like you do...impressiv

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PIII450@465,P2b,128mb,Matrox Mill-G400 32SH,SB.Live !(value),IntelliMouse Explorer (yahoooo! no fu..hm hm. ball any more ...)

[Mark F]

My 2cents-

Is it possible - Probably
Is it likley to be efficiant - Probably not

We will see
Maybe MATROX can/will prove me wrong?
Hope so

Mark F.

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OH NO, my retractable cup holder swallowed a CD

[Unam]

Just re-reading my last post. (I do that now and then ) Matrox will of course say nothing about nothing, this is their usual PR tactic and after their G200 OGL fiasco I can't fault them for that. Although it would be nice... sigh.

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Asus P3B-F1, PIII 600B, 128Mb PC133 RAM, 18.2 KA drive, HP CDRW & Travan drive, SB64PCI, Intel EPro+ PnP NIC, G400.

[franksch3]

I had a look at the WARP development kit from Matrox. It contains several C++ .h files containing hexadecimal values representing microcode for the WARP engine to perform different tasks.

In the document they describe how to use it, but had no time yet to read it thorough. However, looking at the vertex structure you can pass to the microcode, it is possible to do at least transformation on the WARP engine.

The question remains is how fast is it using the WARP engine. Probably not fast enough or else the drivers would have used it. Only way to find out is to try it out.

Haig, is there somewhere a discription of assembly (machine) code for the WARP engine? That's missing in the document.

[red2]

It's intentionally missing; Matrox have only released part of the microcode for the WARP engine. It would be nice if all of it were, but the independent driver writers are about to trounce Matrox's Windows drivers even without it.