Polish Parhelia confirmation

[Wombat]

Yes, this forum is here so you guys can speculate about future products. But when you *cough*authoritatively explain how the GF4MX is chosen, when everything you say is a contradiction to KNOWN FACTS, well.


You hear that whooshing sound? That's your credibility plummeting.

WT<B>F</B> does "official version" mean? You can crack open the packaging on a GF4MX and see that it most certainly is not a GF4Ti.

I can't tell if I want you to pull your head out of your ass, or keep stuffing it up there until you asphyxiate yourself.

[Evildead666]

Nice one Wombat.

Jwb, what are you on?

Pluto???

EE is for Electrical Engineer.
I have done 5 years of computer studies @ University and i currently work with computers.(programming and such)

I also did Microelectronics Systems engineering...

Make up whatever u want, but don't go saying that u know more than anyone else...ok?

Sheesh, somebody just woke up after being asleep for a hundred years.

Go on Bunnies, attack!!!

[Damien]

Girls try to keep your skirts on, its just his opinion………

[knirfie]

GIRLS

[Evildead666]

Hmmmmm........

lookit the bunny...yeah.....lookit.

[Pace]

Originally posted by jwb
Why on earth would sombody buy then a 3dfx Alchemy (8 or 16 times VSA100 if my memory serves correctly) if performance sucked.

Why on earth was Voodoo2 (and SLI) so successfully... Because its performance sucked at that time...

NOOO...

SLI was to improve fillrate (at the time), as Wombat said. Now the limits are with memory bandwidth - SLI won't help with this, it just doubles the requirements.

!! Stop replying if you are under NDA then !!

I KNOW... (that i'm not under NDA )

NDA means he can't disclose the secrets he knows. Your errors are not a secret Just accept that Wombat knows more about CPU design, or show some knowledge to the contrary.

P.

PS: Not meant to be a direct attack, but it's just in my mind at the moment...how many people on this (damn ) Internet speak absolute rubbish as if it's the truth? If I'm not sure about something, then I ask the question, "Is SLI better?" - I don't say "SLI is better, always has, always will." Och aye the noo...

[cbman]

Hey Wombat,

This is unrelated to the thread but I was reading an article in the paper about the HP, Compaq courtcase that is going on at the moment...

That s*** affecting you guys in the CPU division at all?

Oh and if you think Core Architecture is exciting, you should have met the guy I was talking to this morning over coffee... he designs Stills for breweries for a living.. how cool is that.

[Joe DeFuria]

SLI was to improve fillrate (at the time), as Wombat said. Now the limits are with memory bandwidth - SLI won't help with this, it just doubles the requirements.

Actually, the beauty of SLI was that it increased bandwidth in lockstep with fill-rate.

With every chip you added to increase fill-rate, you also by definition also added the proportional bandwidth required to utilized that fill-rate.

[Pace]

Yeah...but it doubles the need for bandwidth with the increase, does it not?

Please tell me my statement wasn't a perfect example of a POS

Say 1Gb/s texture transfer...two SLI chips deliver 2Gb/s, but need twice the textures anyway...filling 2Gb/s?

P.

[Novdid]

Yes that is correct Pace.

[jehwuk]

oops double post

[Greebe]

With many of the several of the 3dfx 6000 series cards having now been benchmarked, it is noted that in order to saturate it's fillrate, it would be neccessary to have a 4gHz cpu... that's what is bad about their mutlichip designs

Substantial enough proof of what we say is true.

[jehwuk]

Originally posted by Pace
Yeah...but it doubles the need for bandwidth with the increase, does it not?

Please tell me my statement wasn't a perfect example of a POS

Say 1Gb/s texture transfer...two SLI chips deliver 2Gb/s, but need twice the textures anyway...filling 2Gb/s?

P.

the need for the extra bandwidth is also handled w/ a seperate memory bus connected to the extra chip.
ur right that the need for bandwidth would be doubled with an two chip SLI config, but the two chip SLI config itself consists of double fillrate, double bandwidth.
i think this is what Joe DeFuria is trying to say, that the "needed" extra bandwidth would be no problem.
but having no problem did make a problem , because it had to dedicate equal amount of RAM to each chip(different amount would be inefficient and would make no use of the extra RAM dedicated to the chip with more RAM), and thus the actual video RAM that is being utilized in eace scene would be divided by the #of chips.
V5 5500 consisted of 2 VSA100 had 64MB of memory(did i get it right?), but could be considered as a single chip 32MB card with double the fillrate, double the bandwidth.

personally, i am very against such technology, since room for innovations r still plenty! (Parhelia, i say?!? i hope?!?)

edit: i just saw greebe's post, and thought i should add this. if the chip(that could do SLI) being used alone was already suffering from the bandwidth bottleneck, then the extra amount of bandwidth that was needed to fulfill one chip's fillrate would be a bottleneck for all the each chips on the SLI configuration, and thus be very stupid(a wrong match of fillrate and the bandwidth would be stupid in the first place, just like the budget video cards on the market, limiting memory bandwidth to 64bit)

[Pace]

But Greeby, we could put a dual-core HyperThreaded Quad-SMP 2GHz Xeon in a beowulf cluster and fill it that way man! Get a grip dumb BBz. gEeZ!

[Pace]

the need for the extra bandwidth is also handled w/ a seperate memory bus connected to the extra chip.
ur right that the need for bandwidth would be doubled with an two chip SLI config, but the two chip SLI config itself consists of double fillrate, double bandwidth.

As I said?

And as we've covered, SLI is useless unless we are fillrate limited. We're now bandwidth bandits baby!